The design is optimized for high performance, low latency, low area, low power, and ease of integration.ĭatabookDesignWare Cores HBM2 PHY Databook for TSMC16FFPC18 (PHY Version: 1. The PUB provides the PHY configuration registers, training algorithms, and BIST features of the interface. The hard macrocells include integrated application-specific HBM2/HBM2E I/Os required for HBM2/HBM2E signaling and are easily assembled into a complete 512- or 1,024-bit HBM2/HBM2E PHY. The DesignWare HBM2/HBM2E PHY is provided as a set of hard macrocells delivered as GDSII along with a soft PHY Utility Block (PUB). In addition, DesignWare HBM IP is in volume production with numerous customer SoCs. The DesignWare HBM2/HBM2E IP solution leverages elements from Synopsys’ silicon-proven DDR4 IP, which has been validated in hundreds of designs and shipped in millions of systems-on-chips (SoCs), enabling designers to lower integration risk and accelerate adoption of the new standard. In addition, the DesignWare HBM2/HBM2E IP solution delivers approximately 10X better energy efficiency than DDR4.
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The broad DesignWare IP portfolio includes logic libraries, embedded.
DESIGNWARE SYNOPSYS VERIFICATION
The complete DesignWare HBM2/HBM2E IP solution includes controller, PHY and verification IP, enabling designers to achieve up to 460 GBps aggregate bandwidth, which is over 14 times the bandwidth of a 72-bit DDR4 interface operating at up to 3200 Mbps. Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. Using the DesignWare Library's Datapath and Building Block IP allows transparent, high-level optimization of performance during synthesis. With the DesignWare HBM2/HBM2E IP solution, designers can achieve their memory throughput requirements with minimal power consumption and low latency. The DesignWare Library's Datapath and Building Block IP is a collection of reusable intellectual property blocks that are tightly integrated into the Synopsys synthesis environment.
![designware synopsys designware synopsys](https://www.synopsys.com/dw/images/ds/arc_em_sdp.jpg)
Advanced graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the increasing compute performance brought by advanced process technologies.